; CC7A Ver 1.0D, Copyright (c) B Knudsen Data ; C compiler for the PIC18 microcontrollers ; ************ 24. Feb 2011 12:28 ************* processor 17C766 radix DEC PRODL EQU 0x18 PRODH EQU 0x19 WREG EQU 0x0A Carry EQU 0 Zero_ EQU 2 PA0 EQU 5 FpFlags EQU 0x2A FpOverflow EQU 1 FpUnderFlow EQU 2 FpDiv0 EQU 3 FpRounding EQU 6 arg1f24 EQU 0x20 arg2f24 EQU 0x23 aarg EQU 0x26 sign EQU 0x28 tmpL EQU 0x29 aarg_2 EQU 0x26 sign_2 EQU 0x28 counter EQU 0x29 xtra EQU 0x26 temp EQU 0x27 expo EQU 0x28 sign_3 EQU 0x29 expo_2 EQU 0x26 xtra_2 EQU 0x27 sign_4 EQU 0x28 rval EQU 0x20 sign_6 EQU 0x26 expo_4 EQU 0x27 xtra_4 EQU 0x28 rval_3 EQU 0x20 ad_data EQU 0x2B tx EQU 0x120 av EQU 0x123 mg EQU 0x126 a EQU 0x129 vx EQU 0x12C prev EQU 0x220 kp EQU 0x223 GOTO main ; FILE 17\demo-fpm.c ; ;#pragma chip PIC17C766 // select device ; ;// FIRST ADD THE INTERRUPT ROUTINE (if any) ;// #include "app-int.c" ; ;#pragma rambank 0 ;#pragma codepage 1 ORG 0x2000 ; FILE 18\math24f.h ;// ************************************************* ;// 24 bit basic floating point math operations ;// Copyright (c) B Knudsen Data, Norway, 2000 - 2005 ;// ************************************************* ; ;#pragma library 1 ;/* PROTOTYPES for page definition in application header file: ;float24 operator* _fmul24( float24 arg1f24, float24 arg2f24); ;float24 operator/ _fdiv24( float24 arg1f24, float24 arg2f24); ;float24 operator+ _fadd24( float24 arg1f24, float24 arg2f24); ;float24 operator- _fsub24( float24 arg1f24, float24 arg2f24); ;float24 operator= _int24ToFloat24( int24 arg1f24); ;float24 operator= _int32ToFloat24( int32 arg32); ;int24 operator= _float24ToInt24( float24 arg1f24); ;bit operator< _f24_LT_f24( float24 arg1f24, float24 arg2f24); ;bit operator>= _f24_GE_f24( float24 arg1f24, float24 arg2f24); ;bit operator> _f24_GT_f24( float24 arg1f24, float24 arg2f24); ;bit operator<= _f24_LE_f24( float24 arg1f24, float24 arg2f24); ;*/ ; ;// DEFINABLE SYMBOLS (in the application code): ;//#define FP_OPTIM_SPEED // optimize for SPEED: default ;//#define FP_OPTIM_SIZE // optimize for SIZE ;//#define DISABLE_ROUNDING // disable rounding and save code space ; ;#define float24ToIEEE754(a) { a.mid8=rl(a.mid8); a.high8=rr(a.high8);\ ; a.mid8=rr(a.mid8); } ;#define IEEE754ToFloat24(a) { a.mid8=rl(a.mid8); a.high8=rl(a.high8);\ ; a.mid8=rr(a.mid8); } ; ; ;/* 24 bit floating point format: ; ; address ID ; X a.low8 : LSB, bit 0-7 of mantissa ; X+1 a.mid8 : bit 8-14 of mantissa, bit 15 is the sign bit ; X+2 a.high8 : MSB, bit 0-7 of exponent, with bias 0x7F ; ; bit 15 of mantissa is a hidden bit, always equal to 1 ; zero (0.0) : a.high8 = 0 (mantissa & sign ignored) ; ; MSB LSB ; 7F 00 00 : 1.0 = 1.0 * 2**(0x7F-0x7F) = 1.0 * 1 ; 7F 80 00 : -1.0 = -1.0 * 2**(0x7F-0x7F) = -1.0 * 1 ; 80 00 00 : 2.0 = 1.0 * 2**(0x80-0x7F) = 1.0 * 2 ; 80 40 00 : 3.0 = 1.5 * 2**(0x80-0x7F) = 1.5 * 2 ; 7E 60 00 : 0.875 = 1.75 * 2**(0x7E-0x7F) = 1.75 * 0.5 ; 7F 60 00 : 1.75 = 1.75 * 2**(0x7E-0x7F) = 1.75 * 1 ; 7F 7F FF : 1.999969482 ; 00 7C 5A : 0.0 (mantissa & sign ignored) ; 01 00 00 : 1.17549435e-38 = 1.0 * 2**(0x01-0x7F) ; FE 7F FF : 3.40277175e+38 = 1.999969482 * 2**(0xFE-0x7F) ; FF 00 00 : +INF : positive infinity ; FF 80 00 : -INF : negative infinity ;*/ ; ;#define FpBIAS 0x7F ; ;#ifndef FpFlags_defined ; #define FpFlags_defined ; ; char FpFlags; ; //bit IOV @ FpFlags.0; // integer overflow flag: NOT USED ; bit FpOverflow @ FpFlags.1; // floating point overflow flag ; bit FpUnderFlow @ FpFlags.2; // floating point underflow flag ; bit FpDiv0 @ FpFlags.3; // floating point divide by zero flag ; //bit FpNAN @ FpFlags.4; // not-a-number exception flag: NOT USED ; bit FpDomainError @ FpFlags.5; // domain error exception flag ; bit FpRounding @ FpFlags.6; // floating point rounding flag, 0=truncation ; // 1 = unbiased rounding to nearest LSB ; //bit FpSaturate @ FpFlags.7; // floating point saturate flag: NOT USED ; ; #pragma floatOverflow FpOverflow ; #pragma floatUnderflow FpUnderFlow ; ; #define InitFpFlags() FpFlags = 0x40 /* enable rounding as default */ ;#endif ; ;#ifdef DISABLE_ROUNDING ; #pragma floatRounding 0 ;#endif ; ; ;#if __CoreSet__ < 1600 ; #define genAdd(r,a) W=a; btsc(Carry); W=incsz(a); r+=W ; #define genSub(r,a) W=a; btss(Carry); W=incsz(a); r-=W ; #define genAddW(r,a) W=a; btsc(Carry); W=incsz(a); W=r+W ; #define genSubW(r,a) W=a; btss(Carry); W=incsz(a); W=r-W ;#else ; #define genAdd(r,a) W=a; r=addWFC(r) ; #define genSub(r,a) W=a; r=subWFB(r) ; #define genAddW(r,a) W=a; W=addWFC(r) ; #define genSubW(r,a) W=a; W=subWFB(r) ;#endif ; ;#if __CoreSet__ == 1700 || __CoreSet__ == 1800 ; #define hw_mult8x8(a,b) W = a; multiply(b) ; #define loRES PRODL ; #define hiRES PRODH ;#endif ; ;#if __CoreSet__ == 2000 ; #define hw_mult8x8(a,b) W = a; multiply(b) ; #define loRES W ; #define hiRES MULH ;#endif ; ; ;float24 operator* _fmul24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _fmul24 ; uns16 aarg; ; W = arg1f24.mid8; MOVFP arg1f24+1,WREG ; aarg.high8 = W; MOVWF aarg+1 ; ; // save sign ; char sign = arg2f24.mid8 ^ W; // before first overflow test XORWF arg2f24+1,W MOVWF sign ; ; W = arg1f24.high8; MOVFP arg1f24+2,WREG ; #if __CoreSet__ / 100 == 17 ; if (W != 0) XORLW 0 BTFSS 0x04,Zero_ ; W = arg2f24.high8; MOVFP arg2f24+2,WREG ; if (W == 0) XORLW 0 BTFSC 0x04,Zero_ ; goto RES0; GOTO m006 ; #else ; if (!Zero_) ; W = arg2f24.high8; ; if (Zero_) ; goto RES0; ; #endif ; ; arg1f24.high8 += W /* arg2f24.high8 */; ADDWF arg1f24+2,1 ; W = FpBIAS-1; MOVLW 126 ; if (Carry) { BTFSS 0x04,Carry GOTO m001 ; arg1f24.high8 -= W; SUBWF arg1f24+2,1 ; if (Carry) BTFSS 0x04,Carry GOTO m002 ; goto OVERFLOW; GOTO m007 ; } ; else { ; arg1f24.high8 -= W; m001 SUBWF arg1f24+2,1 ; if (!Carry) BTFSS 0x04,Carry ; goto UNDERFLOW; GOTO m005 ; } ; aarg.low8 = arg1f24.low8; m002 MOVFP arg1f24,WREG MOVWF aarg ; ; aarg.15 = 1; BSF aarg+1,7 ; arg2f24.15 = 1; BSF arg2f24+1,7 ; ; #if defined hw_mult8x8 && !defined FP_OPTIM_SIZE ; ; char tmpL; ; arg1f24.low16 = 0; CLRF arg1f24,1 CLRF arg1f24+1,1 ; ; hw_mult8x8( arg2f24.low8, aarg.low8); // p1 MOVFP arg2f24,WREG MULWF aarg ; tmpL = hiRES; MOVPF PRODH,tmpL ; ; hw_mult8x8( arg2f24.mid8, aarg.low8); // p2 MOVFP arg2f24+1,WREG MULWF aarg ; tmpL += loRES; MOVFP PRODL,WREG ADDWF tmpL,1 ; genAdd( arg1f24.low8, hiRES); MOVFP PRODH,WREG ADDWFC arg1f24,1 ; genAdd( arg1f24.mid8, 0); MOVLW 0 ADDWFC arg1f24+1,1 ; ; hw_mult8x8( arg2f24.low8, aarg.mid8); // p2 MOVFP arg2f24,WREG MULWF aarg+1 ; tmpL += loRES; MOVFP PRODL,WREG ADDWF tmpL,1 ; genAdd( arg1f24.low8, hiRES); MOVFP PRODH,WREG ADDWFC arg1f24,1 ; genAdd( arg1f24.mid8, 0); MOVLW 0 ADDWFC arg1f24+1,1 ; ; hw_mult8x8( arg2f24.mid8, aarg.mid8); // p3 MOVFP arg2f24+1,WREG MULWF aarg+1 ; arg1f24.low8 += loRES; MOVFP PRODL,WREG ADDWF arg1f24,1 ; genAdd( arg1f24.mid8, hiRES); MOVFP PRODH,WREG ADDWFC arg1f24+1,1 ; ; #undef hw_mult8x8 ; #undef loRES ; #undef hiRES ; ; if (!arg1f24.15) { BTFSC arg1f24+1,7 GOTO m004 ; tmpL = rl( tmpL); RLCF tmpL,1 ; arg1f24.low16 = rl( arg1f24.low16); RLCF arg1f24,1 RLCF arg1f24+1,1 ; if (arg1f24.high8 == 0) TSTFSZ arg1f24+2 GOTO m003 ; goto UNDERFLOW; GOTO m005 ; arg1f24.high8 -= 1; m003 DECF arg1f24+2,1 ; W = rl( tmpL); // restore bit behind LSB in Carry RLCF tmpL,W ; } ; ; #else ; ; arg1f24.low16 = 0; ; ; char counter = sizeof(aarg)*8; ; ; do { ; aarg = rr( aarg); ; if (Carry) { ; arg1f24.low8 += arg2f24.low8; ; genAdd( arg1f24.mid8, arg2f24.mid8); ; } ; arg1f24.low16 = rr( arg1f24.low16); ; counter = decsz(counter); ; } while (1); ; ; if (!arg1f24.15) { ; // catch Carry bit that was shifted out previously ; arg1f24.low16 = rl( arg1f24.low16); ; if (arg1f24.high8 == 0) ; goto UNDERFLOW; ; arg1f24.high8 -= 1; ; W = rl( aarg.high8); ; // restore bit behind LSB in Carry ; } ; ; #endif ; ; #ifndef DISABLE_ROUNDING ; if (FpRounding && Carry) { m004 BTFSS 0x2A,FpRounding GOTO m009 BTFSS 0x04,Carry GOTO m009 ; arg1f24.low8 += 1; INCFSZ arg1f24,1 ; if (!arg1f24.low8) { GOTO m009 ; arg1f24.mid8 += 1; INCFSZ arg1f24+1,1 ; if (!arg1f24.mid8) { GOTO m009 ; #if __CoreSet__ >= 1700 && __CoreSet__ <= 1800 ; Carry = 1; // previous INCF changes Carry BSF 0x04,Carry ; #else ; // Carry = 1; //OK ; #endif ; arg1f24.low16 = rr( arg1f24.low16); RRCF arg1f24+1,1 RRCF arg1f24,1 ; arg1f24.high8 += 1; INCFSZ arg1f24+2,1 ; if (Zero_) GOTO m009 ; goto OVERFLOW; GOTO m007 ; } ; } ; } ; #endif ; goto SET_SIGN; ; ; UNDERFLOW: ; FpUnderFlow = 1; m005 BSF 0x2A,FpUnderFlow ; RES0: ; arg1f24.high8 = 0; m006 CLRF arg1f24+2,1 ; goto MANTISSA; GOTO m008 ; ; OVERFLOW: ; FpOverflow = 1; m007 BSF 0x2A,FpOverflow ; arg1f24.high8 = 0xFF; SETF arg1f24+2,1 ; MANTISSA: ; arg1f24.low16 = 0x8000; m008 CLRF arg1f24,1 MOVLW 128 MOVWF arg1f24+1 ; ; SET_SIGN: ; if (!(sign & 0x80)) m009 BTFSS sign,7 ; arg1f24.15 = 0; BCF arg1f24+1,7 ; return arg1f24; MOVFP arg1f24,WREG RETURN ;} ; ; ; ;float24 operator/ _fdiv24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _fdiv24 ; uns16 aarg; ; W = arg1f24.mid8; MOVFP arg1f24+1,WREG ; aarg.high8 = W; MOVWF aarg_2+1 ; ; // save sign ; char sign = arg2f24.mid8 ^ W; // before first overflow test XORWF arg2f24+1,W MOVWF sign_2 ; ; #if __CoreSet__ / 100 == 17 ; if (!arg2f24.high8) TSTFSZ arg2f24+2 GOTO m010 ; goto Div0; GOTO m023 ; #else ; W = arg2f24.high8; ; if (Zero_) ; goto Div0; ; #endif ; if (!arg1f24.high8) m010 TSTFSZ arg1f24+2 GOTO m011 ; goto RES0; GOTO m025 ; ; arg1f24.high8 -= arg2f24.high8; m011 MOVFP arg2f24+2,WREG SUBWF arg1f24+2,1 ; W = FpBIAS; MOVLW 127 ; if (!Carry) { BTFSC 0x04,Carry GOTO m012 ; arg1f24.high8 += W; ADDWF arg1f24+2,1 ; if (!Carry) BTFSC 0x04,Carry GOTO m013 ; goto UNDERFLOW; GOTO m024 ; } ; else { ; arg1f24.high8 += W; m012 ADDWF arg1f24+2,1 ; if (Carry) BTFSC 0x04,Carry ; goto OVERFLOW; GOTO m026 ; } ; ; aarg.low8 = arg1f24.low8; m013 MOVFP arg1f24,WREG MOVWF aarg_2 ; aarg.15 = 1; BSF aarg_2+1,7 ; arg2f24.15 = 1; BSF arg2f24+1,7 ; ; // division: shift & add ; char counter = 16; MOVLW 16 MOVWF counter ; arg1f24.low16 = 0; // speedup CLRF arg1f24,1 CLRF arg1f24+1,1 ; ;#if defined FP_OPTIM_SPEED || !defined FP_OPTIM_SIZE // SPEED ; ; goto START_ML; GOTO m016 ; ; TEST_ZERO_L: ; W = aarg.low8 - arg2f24.low8; m014 MOVFP arg2f24,WREG SUBWF aarg_2,W ; if (!Carry) BTFSS 0x04,Carry ; goto SHIFT_IN_CARRY; GOTO m019 ; aarg.low8 = W; MOVWF aarg_2 ; aarg.high8 = 0; CLRF aarg_2+1,1 ; goto SET_AND_SHIFT_IN_CARRY; GOTO m018 ; ;// MAIN LOOP ; do { ; LOOP_ML: ; if (!Carry) { m015 BTFSC 0x04,Carry GOTO m017 ; START_ML: ; W = aarg.high8 - arg2f24.mid8; m016 MOVFP arg2f24+1,WREG SUBWF aarg_2+1,W ; if (Zero_) BTFSC 0x04,Zero_ ; goto TEST_ZERO_L; GOTO m014 ; if (!Carry) BTFSS 0x04,Carry ; goto SHIFT_IN_CARRY; GOTO m019 ; } ; aarg.low8 -= arg2f24.low8; m017 MOVFP arg2f24,WREG SUBWF aarg_2,1 ; genSub( aarg.high8, arg2f24.mid8); MOVFP arg2f24+1,WREG SUBWFB aarg_2+1,1 ; SET_AND_SHIFT_IN_CARRY: ; Carry = 1; m018 BSF 0x04,Carry ; SHIFT_IN_CARRY: ; arg1f24.low16 = rl( arg1f24.low16); m019 RLCF arg1f24,1 RLCF arg1f24+1,1 ; // Carry = 0; // ok, speedup ; aarg = rl( aarg); RLCF aarg_2,1 RLCF aarg_2+1,1 ; counter = decsz(counter); DECFSZ counter,1 ; } while (1); GOTO m015 ; ; ; ;#else // SIZE ; ; goto START_ML; ; ;// MAIN LOOP ; do { ; LOOP_ML: ; if (Carry) ; goto SUBTRACT; ; START_ML: ; W = aarg.low8 - arg2f24.low8; ; genSubW( aarg.high8, arg2f24.mid8); ; if (!Carry) ; goto SKIP_SUB; ; SUBTRACT: ; aarg.low8 -= arg2f24.low8; ; genSub( aarg.high8, arg2f24.mid8); ; Carry = 1; ; SKIP_SUB: ; arg1f24.low16 = rl( arg1f24.low16); ; // Carry = 0; // ok ; aarg = rl( aarg); ; counter = decsz(counter); ; } while (1); ; ;#endif ; ; if (!arg1f24.15) { BTFSC arg1f24+1,7 GOTO m021 ; if (!arg1f24.high8) TSTFSZ arg1f24+2 GOTO m020 ; goto UNDERFLOW; GOTO m024 ; #if __CoreSet__ >= 1700 && __CoreSet__ <= 1800 ; sign = rr( sign); // Save Carry m020 RRCF sign_2,1 ; #endif ; arg1f24.high8 --; DECF arg1f24+2,1 ; counter ++; INCF counter,1 ; #if __CoreSet__ >= 1700 && __CoreSet__ <= 1800 ; sign = rl( sign); // Restore Carry, changed by INCF/DECF RLCF sign_2,1 ; #endif ; goto LOOP_ML; GOTO m015 ; } ; ; #ifndef DISABLE_ROUNDING ; if (FpRounding) { m021 BTFSS 0x2A,FpRounding GOTO m029 ; if (Carry) BTFSC 0x04,Carry ; goto ADD_1; GOTO m022 ; aarg.low8 -= arg2f24.low8; MOVFP arg2f24,WREG SUBWF aarg_2,1 ; genSub( aarg.high8, arg2f24.mid8); MOVFP arg2f24+1,WREG SUBWFB aarg_2+1,1 ; if (Carry) { BTFSS 0x04,Carry GOTO m029 ; ADD_1: ; arg1f24.low8 += 1; m022 INCFSZ arg1f24,1 ; if (!arg1f24.low8) { GOTO m029 ; arg1f24.mid8 ++; INCFSZ arg1f24+1,1 ; if (!arg1f24.mid8) { GOTO m029 ; arg1f24.low16 = rr( arg1f24.low16); RRCF arg1f24+1,1 RRCF arg1f24,1 ; arg1f24.high8 ++; INCFSZ arg1f24+2,1 ; if (!arg1f24.high8) GOTO m029 ; goto OVERFLOW; GOTO m026 ; } ; } ; } ; } ; #endif ; goto SET_SIGN; ; ; Div0: ; FpDiv0 = 1; m023 BSF 0x2A,FpDiv0 ; goto SATURATE; GOTO m027 ; ; UNDERFLOW: ; FpUnderFlow = 1; m024 BSF 0x2A,FpUnderFlow ; RES0: ; arg1f24.high8 = 0; m025 CLRF arg1f24+2,1 ; goto MANTISSA; GOTO m028 ; ; OVERFLOW: ; FpOverflow = 1; m026 BSF 0x2A,FpOverflow ; SATURATE: ; arg1f24.high8 = 0xFF; m027 SETF arg1f24+2,1 ; MANTISSA: ; arg1f24.low16 = 0x8000; m028 CLRF arg1f24,1 MOVLW 128 MOVWF arg1f24+1 ; ; SET_SIGN: ; if (!(sign & 0x80)) m029 BTFSS sign_2,7 ; arg1f24.15 = 0; BCF arg1f24+1,7 ; return arg1f24; MOVFP arg1f24,WREG RETURN ;} ; ; ;float24 operator+ _fadd24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _fadd24 ; char xtra, temp; ; char expo = arg1f24.high8 - arg2f24.high8; MOVFP arg2f24+2,WREG SUBWF arg1f24+2,W MOVWF expo ; if (!Carry) { BTFSC 0x04,Carry GOTO m030 ; expo = -expo; NEGW expo,1 ; temp = arg1f24.high8; MOVFP arg1f24+2,WREG MOVWF temp ; arg1f24.high8 = arg2f24.high8; MOVFP arg2f24+2,WREG MOVWF arg1f24+2 ; arg2f24.high8 = temp; MOVFP temp,WREG MOVWF arg2f24+2 ; temp = arg1f24.mid8; MOVFP arg1f24+1,WREG MOVWF temp ; arg1f24.mid8 = arg2f24.mid8; MOVFP arg2f24+1,WREG MOVWF arg1f24+1 ; arg2f24.mid8 = temp; MOVFP temp,WREG MOVWF arg2f24+1 ; temp = arg1f24.low8; MOVFP arg1f24,WREG MOVWF temp ; arg1f24.low8 = arg2f24.low8; MOVFP arg2f24,WREG MOVWF arg1f24 ; arg2f24.low8 = temp; MOVFP temp,WREG MOVWF arg2f24 ; } ; if (expo > sizeof(arg1f24)*8-7) m030 MOVLW 18 CPFSLT expo ; goto _RETURN_MF; GOTO m050 ; if (!arg2f24.high8) TSTFSZ arg2f24+2 GOTO m031 ; goto _RETURN_MF; // result is arg1f24 GOTO m050 ; ; xtra = 0; m031 CLRF xtra,1 ; ; W = arg1f24.mid8; MOVFP arg1f24+1,WREG ; temp = W; MOVWF temp ; char sign = arg2f24.mid8 ^ W; XORWF arg2f24+1,W MOVWF sign_3 ; arg1f24.15 = 1; BSF arg1f24+1,7 ; arg2f24.15 = 1; BSF arg2f24+1,7 ; ; while (1) { ; W = 8; m032 MOVLW 8 ; expo -= W; SUBWF expo,1 ; if (!Carry) BTFSS 0x04,Carry ; break; GOTO m033 ; xtra = arg2f24.low8; MOVFP arg2f24,WREG MOVWF xtra ; arg2f24.low8 = arg2f24.mid8; MOVFP arg2f24+1,WREG MOVWF arg2f24 ; arg2f24.mid8 = 0; CLRF arg2f24+1,1 ; } GOTO m032 ; expo += W; m033 ADDWF expo,1 ; if (expo) { TSTFSZ expo GOTO m034 GOTO m035 ; do { ; Carry = 0; m034 BCF 0x04,Carry ; arg2f24.low16 = rr( arg2f24.low16); RRCF arg2f24+1,1 RRCF arg2f24,1 ; xtra = rr( xtra); RRCF xtra,1 ; } while (--expo > 0); DECFSZ expo,1 GOTO m034 ; } ; ; ; if (sign & 0x80) { m035 BTFSS sign_3,7 GOTO m042 ; // SUBTRACT ; arg1f24.low8 -= arg2f24.low8; MOVFP arg2f24,WREG SUBWF arg1f24,1 ; genSub( arg1f24.mid8, arg2f24.mid8); MOVFP arg2f24+1,WREG SUBWFB arg1f24+1,1 ; if (!Carry) { // arg2f24 > arg1f24 BTFSC 0x04,Carry GOTO m036 ; arg1f24.low16 = -arg1f24.low16; COMF arg1f24+1,1 COMF arg1f24,1 INCF arg1f24,1 MOVLW 0 ADDWFC arg1f24+1,1 ; // xtra == 0 because arg1f24.exp == arg2f24.exp ; temp ^= 0x80; // invert sign MOVLW 128 XORWF temp,1 ; } ; xtra = -xtra; m036 MOVFP xtra,WREG NEGW xtra,1 ; if (xtra) TSTFSZ xtra GOTO m037 GOTO m038 ; arg1f24.low16 --; m037 DECF arg1f24,1 MOVLW 0 SUBWFB arg1f24+1,1 ; // adjust result left ; #define counter expo ; counter = 3; m038 MOVLW 3 MOVWF expo ; while (!arg1f24.mid8) { m039 TSTFSZ arg1f24+1 GOTO m040 ; arg1f24.mid8 = arg1f24.low8; MOVFP arg1f24,WREG MOVWF arg1f24+1 ; arg1f24.low8 = xtra; MOVFP xtra,WREG MOVWF arg1f24 ; xtra = 0; CLRF xtra,1 ; arg1f24.high8 -= 8; MOVLW 8 SUBWF arg1f24+2,1 ; if (!Carry) BTFSS 0x04,Carry ; goto RES0; GOTO m046 ; if (--counter == 0) // max 2 iterations DECFSZ expo,1 GOTO m039 ; goto RES0; GOTO m046 ; } ; #undef counter ; while (!arg1f24.15) { m040 BTFSC arg1f24+1,7 GOTO m041 ; Carry = 0; BCF 0x04,Carry ; xtra = rl( xtra); RLCF xtra,1 ; arg1f24.low16 = rl( arg1f24.low16); RLCF arg1f24,1 RLCF arg1f24+1,1 ; arg1f24.high8 --; DECFSZ arg1f24+2,1 ; if (!arg1f24.high8) GOTO m040 ; goto RES0; // UNDERFLOW? GOTO m046 ; } ; #ifndef DISABLE_ROUNDING ; if (FpRounding && (xtra & 0x80)) { m041 BTFSS 0x2A,FpRounding GOTO m049 BTFSS xtra,7 GOTO m049 ; xtra = 0; // disable recursion CLRF xtra,1 ; goto INCREMENT; GOTO m045 ; } ; #endif ; } ; else { ; // ADD arg1f24 and arg2f24 ; arg1f24.low8 += arg2f24.low8; m042 MOVFP arg2f24,WREG ADDWF arg1f24,1 ; genAdd( arg1f24.mid8, arg2f24.mid8); MOVFP arg2f24+1,WREG ADDWFC arg1f24+1,1 ; if (Carry) { BTFSS 0x04,Carry GOTO m044 ; ADJUST_RIGHT: ; arg1f24.low16 = rr( arg1f24.low16); m043 RRCF arg1f24+1,1 RRCF arg1f24,1 ; xtra = rr( xtra); RRCF xtra,1 ; arg1f24.high8 += 1; // exp INCFSZ arg1f24+2,1 ; if (!arg1f24.high8) GOTO m044 ; goto OVERFLOW; GOTO m047 ; } ; #ifndef DISABLE_ROUNDING ; if (FpRounding && (xtra & 0x80)) { m044 BTFSS 0x2A,FpRounding GOTO m049 BTFSS xtra,7 GOTO m049 ; INCREMENT: ; arg1f24.low8 += 1; m045 INCFSZ arg1f24,1 ; if (!arg1f24.low8) { GOTO m049 ; arg1f24.mid8 += 1; INCFSZ arg1f24+1,1 ; if (!arg1f24.mid8) { GOTO m049 ; Carry = 1; // prepare for shift BSF 0x04,Carry ; arg1f24.0 = 0; // disable recursion BCF arg1f24,0 ; goto ADJUST_RIGHT; GOTO m043 ; } ; } ; } ; #endif ; } ; goto SET_SIGN; ; ;// UNDERFLOW: ;// FpUnderFlow = 1; ; RES0: ; arg1f24.high8 = 0; m046 CLRF arg1f24+2,1 ; goto MANTISSA; GOTO m048 ; ; OVERFLOW: ; FpOverflow = 1; m047 BSF 0x2A,FpOverflow ; arg1f24.high8 = 0xFF; SETF arg1f24+2,1 ; MANTISSA: ; arg1f24.low16 = 0x8000; m048 CLRF arg1f24,1 MOVLW 128 MOVWF arg1f24+1 ; ; SET_SIGN: ; if (!(temp & 0x80)) m049 BTFSS temp,7 ; arg1f24.15 = 0; BCF arg1f24+1,7 ; ; _RETURN_MF: ; return arg1f24; m050 MOVFP arg1f24,WREG RETURN ;} ; ; ;// SUBTRACTION ; ;float24 operator- _fsub24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _fsub24 ; arg2f24.mid8 ^= 0x80; ; arg1f24 += arg2f24; ; return arg1f24; ;} ; ; ;float24 operator=( int8 arg) @ ;float24 operator=( uns8 arg) @ ;float24 operator=( int16 arg) @ ;float24 operator=( uns16 arg) @ ;float24 operator= _int24ToFloat24( sharedM int24 arg1f24) ;{ _int24ToFloat24 ; sharedM float24 arg2f24; // unused, but required ; char expo = FpBIAS + 16 - 1; MOVLW 142 MOVWF expo_2 ; char xtra = 0; CLRF xtra_2,1 ; char sign = 0; CLRF sign_4,1 ; if (arg1f24 < 0) { BTFSS arg1f24+2,7 GOTO m051 ; arg1f24 = -arg1f24; COMF arg1f24+2,1 COMF arg1f24+1,1 COMF arg1f24,1 INCF arg1f24,1 MOVLW 0 ADDWFC arg1f24+1,1 ADDWFC arg1f24+2,1 ; sign |= 0x80; BSF sign_4,7 ; } ; if (arg1f24.high8) { m051 TSTFSZ arg1f24+2 GOTO m052 GOTO m053 ; expo += 8; m052 MOVLW 8 ADDWF expo_2,1 ; xtra = arg1f24.low8; MOVFP arg1f24,WREG MOVWF xtra_2 ; arg1f24.low8 = arg1f24.mid8; MOVFP arg1f24+1,WREG MOVWF arg1f24 ; arg1f24.mid8 = arg1f24.high8; MOVFP arg1f24+2,WREG MOVWF arg1f24+1 ; } ; else if (!arg1f24.mid8) { GOTO m055 m053 TSTFSZ arg1f24+1 GOTO m055 ; expo -= 8; MOVLW 8 SUBWF expo_2,1 ; W = arg1f24.low8; MOVFP arg1f24,WREG ; if (!W) XORLW 0 BTFSC 0x04,Zero_ ; goto _RETURN_MF; GOTO m057 ; arg1f24.mid8 = W; MOVWF arg1f24+1 ; arg1f24.low8 = 0; CLRF arg1f24,1 ; } ; ; // arg1f24.mid8 != 0 ; goto TEST_ARG1_B15; GOTO m055 ; do { ; xtra = rl( xtra); m054 RLCF xtra_2,1 ; arg1f24.low16 = rl( arg1f24.low16); RLCF arg1f24,1 RLCF arg1f24+1,1 ; expo --; DECF expo_2,1 ; TEST_ARG1_B15: ; } while (!arg1f24.15); m055 BTFSS arg1f24+1,7 GOTO m054 ; ; #ifndef DISABLE_ROUNDING ; if (FpRounding && (xtra & 0x80)) { BTFSS 0x2A,FpRounding GOTO m056 BTFSS xtra_2,7 GOTO m056 ; arg1f24.low8 += 1; INCFSZ arg1f24,1 ; if (!arg1f24.low8) { GOTO m056 ; arg1f24.mid8 += 1; INCFSZ arg1f24+1,1 ; if (!arg1f24.mid8) { GOTO m056 ; Carry = 1; BSF 0x04,Carry ; arg1f24.low16 = rr( arg1f24.low16); RRCF arg1f24+1,1 RRCF arg1f24,1 ; expo ++; INCF expo_2,1 ; } ; } ; } ; #endif ; ; arg1f24.high8 = expo; m056 MOVFP expo_2,WREG MOVWF arg1f24+2 ; if (!(sign & 0x80)) BTFSS sign_4,7 ; arg1f24.15 = 0; BCF arg1f24+1,7 ; ; _RETURN_MF: ; float24 rval @ arg1f24; ; rval.low24 = arg1f24.low24; ; return rval; m057 MOVFP rval,WREG RETURN ;} ; ; ;float24 operator=( uns24 arg) @ ;float24 operator= _int32ToFloat24( int32 arg32) ;{ _int32ToFloat24 ; char expo = FpBIAS + 16 - 1; ; char xtra @ arg32.high8; ; char sign = 0; ; if (arg32 < 0) { ; arg32 = -arg32; ; sign |= 0x80; ; } ; if (arg32.high8) { ; expo += 8; ; arg32.low8 = arg32.midL8; ; arg32.midL8 = arg32.midH8; ; arg32.midH8 = arg32.high8; ; arg32.high8 = 0; ; } ; if (arg32.midH8) { ; expo += 8; ; xtra = arg32.low8; ; arg32.low8 = arg32.midL8; ; arg32.midL8 = arg32.midH8; ; } ; else if (!arg32.midL8) { ; expo -= 8; ; W = arg32.low8; ; if (!W) ; goto _RETURN_MF; ; arg32.midL8 = W; ; arg32.low8 = 0; ; } ; ; // arg32.midL8 != 0 ; goto TEST_ARG_B15; ; do { ; xtra = rl( xtra); ; arg32.low16 = rl( arg32.low16); ; expo --; ; TEST_ARG_B15: ; } while (!arg32.15); ; ; #ifndef DISABLE_ROUNDING ; if (FpRounding && (xtra & 0x80)) { ; arg32.low8 += 1; ; if (!arg32.low8) { ; arg32.midL8 += 1; ; if (!arg32.midL8) { ; Carry = 1; ; arg32.low16 = rr( arg32.low16); ; expo ++; ; } ; } ; } ; #endif ; ; arg32.midH8 = expo; ; if (!(sign & 0x80)) ; arg32.15 = 0; ; ; _RETURN_MF: ; float24 rval @ arg32; ; rval.low24 = arg32.low24; ; return rval; ;} ; ; ;uns8 operator=( sharedM float24 arg1f24) @ ;int8 operator=( sharedM float24 arg1f24) @ ;uns16 operator=( sharedM float24 arg1f24) @ ;int16 operator=( sharedM float24 arg1f24) @ ;int24 operator= _float24ToInt24( sharedM float24 arg1f24) ;{ _float24ToInt24 ; sharedM float24 arg2f24; // unused, but required ; char sign = arg1f24.mid8; MOVFP arg1f24+1,WREG MOVWF sign_6 ; char expo = arg1f24.high8 - (FpBIAS-1); MOVLW 126 SUBWF arg1f24+2,W MOVWF expo_4 ; if (!Carry) BTFSS 0x04,Carry ; goto RES0; GOTO m063 ; arg1f24.15 = 1; BSF arg1f24+1,7 ; ; arg1f24.high8 = 0; CLRF arg1f24+2,1 ; #ifndef DISABLE_ROUNDING ; char xtra = 0; CLRF xtra_4,1 ; #endif ; ; // (a): expo = 0..8 : shift 1 byte to the right ; // (b): expo = 9..16: shift 0 byte ; // (c): expo = 17..24: shift 1 byte to the left ; #if __CoreSet__ / 100 == 12 ; expo -= 17; ; expo = 0xFF - expo; // COMF (Carry unchanged) ; if (Carry) { // (c) ; #else ; expo = 16 - expo; SUBLW 16 MOVWF expo_4 ; if (!Carry) { // (c) BTFSC 0x04,Carry GOTO m058 ; #endif ; expo += 8; MOVLW 8 ADDWF expo_4,1 ; if (!Carry) BTFSS 0x04,Carry ; goto OVERFLOW; GOTO m062 ; arg1f24.high8 = arg1f24.mid8; MOVFP arg1f24+1,WREG MOVWF arg1f24+2 ; arg1f24.mid8 = arg1f24.low8; MOVFP arg1f24,WREG MOVWF arg1f24+1 ; arg1f24.low8 = 0; CLRF arg1f24,1 ; } ; else { // (a) (b) GOTO m059 ; // expo = 0 .. 16 ; W = expo - 8; m058 MOVLW 8 SUBWF expo_4,W ; if (Carry) { // (a) BTFSS 0x04,Carry GOTO m059 ; expo = W; MOVWF expo_4 ; #ifndef DISABLE_ROUNDING ; xtra = arg1f24.low8; MOVFP arg1f24,WREG MOVWF xtra_4 ; #endif ; arg1f24.low8 = arg1f24.mid8; MOVFP arg1f24+1,WREG MOVWF arg1f24 ; arg1f24.mid8 = 0; CLRF arg1f24+1,1 ; } ; } ; if (expo) { m059 TSTFSZ expo_4 GOTO m060 GOTO m061 ; do { ; Carry = 0; m060 BCF 0x04,Carry ; arg1f24.high8 = rr( arg1f24.high8); RRCF arg1f24+2,1 ; arg1f24.low16 = rr( arg1f24.low16); RRCF arg1f24+1,1 RRCF arg1f24,1 ; #ifndef DISABLE_ROUNDING ; xtra = rr( xtra); RRCF xtra_4,1 ; #endif ; } while (--expo); DECFSZ expo_4,1 GOTO m060 ; } ; if (arg1f24.23) { m061 BTFSS arg1f24+2,7 GOTO m065 ; OVERFLOW: ; FpOverflow = 1; m062 BSF 0x2A,FpOverflow ; W = 0xFF; MOVLW 255 ; goto ASSIGNW; GOTO m064 ; RES0: ; W = 0; m063 MOVLW 0 ; ASSIGNW: ; arg1f24.low8 = W; m064 MOVWF arg1f24 ; arg1f24.mid8 = W; MOVWF arg1f24+1 ; arg1f24.high8 = W; MOVWF arg1f24+2 ; arg1f24.23 = 0; BCF arg1f24+2,7 ; } ; else { GOTO m067 ; #ifndef DISABLE_ROUNDING ; if (FpRounding && (xtra & 0x80)) { m065 BTFSS 0x2A,FpRounding GOTO m066 BTFSS xtra_4,7 GOTO m066 ; arg1f24.low8 += 1; INCFSZ arg1f24,1 ; if (!arg1f24.low8) GOTO m066 ; arg1f24.mid8 += 1; INCF arg1f24+1,1 ; } ; #endif ; if (sign & 0x80) m066 BTFSS sign_6,7 GOTO m067 ; arg1f24.low24 = -arg1f24.low24; COMF arg1f24+2,1 COMF arg1f24+1,1 COMF arg1f24,1 INCF arg1f24,1 MOVLW 0 ADDWFC arg1f24+1,1 ADDWFC arg1f24+2,1 ; } ; int24 rval @ arg1f24; ; rval = arg1f24.low24; ; return rval; m067 MOVFP rval_3,WREG RETURN ;} ; ; ;bit operator< _f24_LT_f24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _f24_LT_f24 ; Carry = 0; ; if (!(arg1f24.high8 | arg2f24.high8)) ; return Carry; ; if (!arg1f24.15) { ; if (arg2f24.15) ; return Carry; ; W = arg1f24.low8 - arg2f24.low8; ; genSubW( arg1f24.mid8, arg2f24.mid8); ; genSubW( arg1f24.high8, arg2f24.high8); ; goto _RETURN_MF; ; } ; if (!arg2f24.15) ; goto _RETURN_MF; ; W = arg2f24.low8 - arg1f24.low8; ; genSubW( arg2f24.mid8, arg1f24.mid8); ; genSubW( arg2f24.high8, arg1f24.high8); ; _RETURN_MF: ; if (Carry) ; return 0; ; return 1; ;} ; ; ;bit operator>= _f24_GE_f24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _f24_GE_f24 ; Carry = 1; ; if (!(arg1f24.high8 | arg2f24.high8)) ; return Carry; ; if (!arg1f24.15) { ; if (arg2f24.15) ; return Carry; ; W = arg1f24.low8 - arg2f24.low8; ; genSubW( arg1f24.mid8, arg2f24.mid8); ; genSubW( arg1f24.high8, arg2f24.high8); ; return Carry; ; } ; Carry = 0; ; if (!arg2f24.15) ; return Carry; ; W = arg2f24.low8 - arg1f24.low8; ; genSubW( arg2f24.mid8, arg1f24.mid8); ; genSubW( arg2f24.high8, arg1f24.high8); ; return Carry; ;} ; ; ; ;bit operator> _f24_GT_f24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _f24_GT_f24 ; Carry = 0; ; if (!(arg1f24.high8 | arg2f24.high8)) ; return Carry; ; if (!arg1f24.15) { ; if (arg2f24.15) ; goto _RETURN_MF; ; W = arg2f24.low8 - arg1f24.low8; ; genSubW( arg2f24.mid8, arg1f24.mid8); ; genSubW( arg2f24.high8, arg1f24.high8); ; goto _RETURN_MF; ; } ; if (!arg2f24.15) ; return Carry; ; W = arg1f24.low8 - arg2f24.low8; ; genSubW( arg1f24.mid8, arg2f24.mid8); ; genSubW( arg1f24.high8, arg2f24.high8); ; _RETURN_MF: ; if (Carry) ; return 0; ; return 1; ;} ; ; ; ;bit operator<= _f24_LE_f24( sharedM float24 arg1f24, sharedM float24 arg2f24) ;{ _f24_LE_f24 ; Carry = 1; ; if (!(arg1f24.high8 | arg2f24.high8)) ; return Carry; ; if (!arg1f24.15) { ; Carry = 0; ; if (arg2f24.15) ; return Carry; ; W = arg2f24.low8 - arg1f24.low8; ; genSubW( arg2f24.mid8, arg1f24.mid8); ; genSubW( arg2f24.high8, arg1f24.high8); ; return Carry; ; } ; if (!arg2f24.15) ; return Carry; ; W = arg1f24.low8 - arg2f24.low8; ; genSubW( arg1f24.mid8, arg2f24.mid8); ; genSubW( arg1f24.high8, arg2f24.high8); ; return Carry; ; FILE 17\demo-fpm.c ;#include "math24f.h" ;#pragma codepage 0 ORG 0x0001 ; ;uns16 ad_data; ;bank1 float tx, av, mg, a, vx; ;bank2 float prev, kp; ; ;void main(void) ;{ main ; InitFpFlags(); // enable rounding as default MOVLW 64 MOVLR 0 MOVWF FpFlags ; vx = 3.127; MOVLW 33 MOVLR 1 MOVWF vx MOVLW 72 MOVWF vx+1 MOVLW 128 MOVWF vx+2 ; tx += ad_data; // automatic type cast MOVLR 0 MOVFP ad_data,WREG MOVWF arg1f24 MOVFP ad_data+1,WREG MOVWF arg1f24+1 CLRF arg1f24+2,1 BSF 0x03,PA0 CALL _int24ToFloat24 MOVLR 1 MOVFP tx,WREG MOVLR 0 MOVWF arg2f24 MOVLR 1 MOVFP tx+1,WREG MOVLR 0 MOVWF arg2f24+1 MOVLR 1 MOVFP tx+2,WREG MOVLR 0 MOVWF arg2f24+2 CALL _fadd24 MOVLR 1 MOVWF tx MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 1 MOVWF tx+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 1 MOVWF tx+2 ; ad_data = kp; // assign integer part MOVLR 2 MOVFP kp,WREG MOVLR 0 MOVWF arg1f24 MOVLR 2 MOVFP kp+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 2 MOVFP kp+2,WREG MOVLR 0 MOVWF arg1f24+2 CALL _float24ToInt24 BCF 0x03,PA0 MOVWF ad_data MOVFP rval_3+1,WREG MOVWF ad_data+1 ; if ( tx < 0) MOVLR 1 MOVFP tx+2,WREG XORLW 0 BTFSC 0x04,Zero_ GOTO m068 BTFSC tx+1,7 ; tx = -tx; // make positive BTG tx+1,7 ; av = tx/20.0; m068 MOVFP tx,WREG MOVLR 0 MOVWF arg1f24 MOVLR 1 MOVFP tx+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 1 MOVFP tx+2,WREG MOVLR 0 MOVWF arg1f24+2 CLRF arg2f24,1 MOVLW 32 MOVWF arg2f24+1 MOVLW 131 MOVWF arg2f24+2 BSF 0x03,PA0 CALL _fdiv24 MOVLR 1 MOVWF av MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 1 MOVWF av+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 1 MOVWF av+2 ; mg = av * 1.25; MOVFP av,WREG MOVLR 0 MOVWF arg1f24 MOVLR 1 MOVFP av+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 1 MOVFP av+2,WREG MOVLR 0 MOVWF arg1f24+2 CLRF arg2f24,1 MOVLW 32 MOVWF arg2f24+1 MOVLW 127 MOVWF arg2f24+2 CALL _fmul24 MOVLR 1 MOVWF mg MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 1 MOVWF mg+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 1 MOVWF mg+2 ; a = mg * 0.98; MOVFP mg,WREG MOVLR 0 MOVWF arg1f24 MOVLR 1 MOVFP mg+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 1 MOVFP mg+2,WREG MOVLR 0 MOVWF arg1f24+2 MOVLW 225 MOVWF arg2f24 MOVLW 122 MOVWF arg2f24+1 MOVLW 126 MOVWF arg2f24+2 CALL _fmul24 MOVLR 1 MOVWF a MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 1 MOVWF a+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 1 MOVWF a+2 ; prev = vx; MOVFP vx,WREG MOVLR 2 MOVWF prev MOVLR 1 MOVFP vx+1,WREG MOVLR 2 MOVWF prev+1 MOVLR 1 MOVFP vx+2,WREG MOVLR 2 MOVWF prev+2 ; vx = a/5.0 + prev; MOVLR 1 MOVFP a,WREG MOVLR 0 MOVWF arg1f24 MOVLR 1 MOVFP a+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 1 MOVFP a+2,WREG MOVLR 0 MOVWF arg1f24+2 CLRF arg2f24,1 MOVLW 32 MOVWF arg2f24+1 MOVLW 129 MOVWF arg2f24+2 CALL _fdiv24 MOVLR 2 MOVFP prev,WREG MOVLR 0 MOVWF arg2f24 MOVLR 2 MOVFP prev+1,WREG MOVLR 0 MOVWF arg2f24+1 MOVLR 2 MOVFP prev+2,WREG MOVLR 0 MOVWF arg2f24+2 CALL _fadd24 MOVLR 1 MOVWF vx MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 1 MOVWF vx+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 1 MOVWF vx+2 ; ; kp = vx * 0.036; MOVFP vx,WREG MOVLR 0 MOVWF arg1f24 MOVLR 1 MOVFP vx+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 1 MOVFP vx+2,WREG MOVLR 0 MOVWF arg1f24+2 MOVLW 117 MOVWF arg2f24 MOVLW 19 MOVWF arg2f24+1 MOVLW 122 MOVWF arg2f24+2 CALL _fmul24 MOVLR 2 MOVWF kp MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 2 MOVWF kp+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 2 MOVWF kp+2 ; kp = vx / (1.0/0.036); MOVLR 1 MOVFP vx,WREG MOVLR 0 MOVWF arg1f24 MOVLR 1 MOVFP vx+1,WREG MOVLR 0 MOVWF arg1f24+1 MOVLR 1 MOVFP vx+2,WREG MOVLR 0 MOVWF arg1f24+2 MOVLW 57 MOVWF arg2f24 MOVLW 94 MOVWF arg2f24+1 MOVLW 131 MOVWF arg2f24+2 CALL _fdiv24 BCF 0x03,PA0 MOVLR 2 MOVWF kp MOVLR 0 MOVFP arg1f24+1,WREG MOVLR 2 MOVWF kp+1 MOVLR 0 MOVFP arg1f24+2,WREG MOVLR 2 MOVWF kp+2 ;} SLEEP GOTO main END ; *** KEY INFO *** ; 0x0001 P0 260 word(s) 3 % : main ; 0x2000 P1 89 word(s) 1 % : _fmul24 ; 0x2059 P1 100 word(s) 1 % : _fdiv24 ; 0x20BD P1 145 word(s) 1 % : _fadd24 ; 0x214E P1 61 word(s) 0 % : _int24ToFloat24 ; 0x218B P1 73 word(s) 0 % : _float24ToInt24 ; RAM usage: 34 bytes (10 local), 868 bytes free ; Maximum call level: 1 ; Codepage 0 has 261 word(s) : 3 % ; Codepage 1 has 468 word(s) : 5 % ; Total of 729 code words (4 %)