CC5X C compiler for PICmicro

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Enhanced 14 bit Core Support

The following table shows the implemented features for the Enhanced 14 bit Core.

Supported 32768 words of code (16 code pages of 2k words code)
Supported 4k byte RAM/SFR addressing (32/64 banks of 128 bytes)
Supported Automatic interrupt context save
Supported 16 level stack
Supported Automatic page updating using new MOVLP instruction
Supported Automatic bank updating using new MOVLB instruction
Supported New aritmethic instructions (ADDWFC, SUBWFB, ASLF, LSLF, LSRF) : supported by code generator and optimizer, and math libraries
Supported Continuous indirect RAM addressing : enables large tables and structures
Supported 16 bit indirect registers
Supported Pre/post inc-/decrement of 16 bit indirect registers
Supported Computed forward branch (BRW) : fast table lookup and fast task switching
Supported WREG addressing
Supported Configuration data at HEX file address 8007h and 8008h
Supported Device ID at HEX file address 8006h
Supported USER ID at HEX file address 8000h - 8003h
Supported EEPROM data at HEX file address : 0xF000 - 0xF0FF
Supported Inline assembly support for new instructions (except BRA)

The collection of header files is available from the download page [complete header file list].

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